1. Field of the Invention
The present invention relates to a static induction transistor and, more particularly, to a static induction transistor which permits prevention of the deterioration of its voltage-withstanding property and its destruction even when a reverse bias voltage higher than its withstand voltage is applied between its gate and drain.
2. Description of the Related Art
A static induction transistor (hereinafter abbreviated to SIT) is easy in its multi-channel version by the use of a vertical structure, thus permitting its operating current to be increased. In addition, the SIT is suited for applications at high power because a withstand voltage between its gate and drain can be increased by insertion of a high-resistivity layer between the gate and drain.
FIG. 1 is a sectional view of a conventional SIT 10.
As shown, an n.sup.- type epitaxial layer 12 is formed on a major surface of an n.sup.+ type silicon substrate 11. On the side of the major surface of n.sup.- epitaxial layer 12 are formed p.sup.+ type gate regions 13 and n.sup.+ type source regions 14. p.sup.+ type gate regions 13 and n.sup.+ type source regions 14 are respectively connected to gate electrodes 16 and source electrodes 17 via contact holes formed by etching an oxide layer 15 formed on n.sup.- type epitaxial layer 12. On the other major surface of n.sup.+ type substrate 11 is formed a drain electrode 18. Gate electrodes 16, source electrodes 17 and drain electrode 18 are made of metal such as aluminum. The n.sup.+ type source region 14 is electrically connected to source electrode 17 by polysilicon 21. In the above structure, a substrate region that is located below n.sup.+ type source region 14 and between p.sup.+ type gate regions 13 forms a channel region 19. The n.sup.- type epitaxial layer 12 and n.sup.+ type substrate 11 form the drain region.
SIT 10 structured as above is a normally-off type of SIT in which channel regions 19 are all depleted of carriers when a forward bias voltage higher than a predetermined voltage is not applied between gate electrode 16 and source electrode 17 and no current flow is produced between the source and drain.
FIGS. 2A and 2B illustrate methods of applying voltages to gate electrode (G) 16, source electrode (S) 17 and drain electrode (D) 18 in measuring the drain-source breakdown voltage (BV.sub.DSS) and the drain-gate breakdown voltage (BV.sub.DGO).
In measuring the drain-source breakdown voltage (BV.sub.DSS), as illustrated in FIG. 2A, an equal voltage is applied to gate electrode 16 and source electrode 17 and a reverse bias voltage Va is applied to gate electrode 16 and drain electrode 18.
In measuring the drain-gate breakdown voltage (BV.sub.DGO), as illustrated in FIG. 2B, a reverse bias voltage Va is applied between gate electrode 16 and drain electrode 18.
As stated above, a reverse voltage is applied between the gate and drain in measuring either of the drain-source breakdown voltage (BV.sub.DSS) and the drain-gate breakdown voltage (BV.sub.DGO). Thus, since the pn junction formed of p.sup.+ type gate region 13 and n.sup.- type epitaxial layer (drain layer) 12 is reverse-biased in measuring either of the drain-source breakdown voltage (BV.sub.DSS) and the drain-gate breakdown voltage (BV.sub.DGO), a depletion layer 20 is widely formed around the pn junction, particularly in n.sup.- type epitaxial layer 12 which has a low impurity concentration. When the reverse bias voltage Va is further increased, depletion layer 20 will reach to the interface between n.sup.- type epitaxial layer 12 and n.sup.+ type substrate 11 as depicted in FIG. 3. When an electric field E at the junction between p.sup.+ type gate region 13 and n.sup.- type epitaxial layer 12, across which the maximum electric field Emax is applied, reaches the critical electric field Ecrit at which avalanche breakdown begins, the avalanche breakdown will occur at the junction between p.sup.+ type gate region 13 and n.sup.- type epitaxial layer 12. As a result, electron-hole pairs are generated suddenly and markedly within depletion layer 20 (the electrons are indicated by black dots, while the holes are indicated by white dots in FIG. 3). Of the generated electron-hole pairs, the electrons are accelerated by the electric field E. within depletion layer 20 so that their energy increase (they become hot electrons), thus causing secondary avalanche breakdown at the interface between n.sup.- type epitaxial layer 12 and n.sup.+ type substrate 11 where there are many crystal defects. Of electron-hole pairs generated at the interface between n.sup.- type epitaxial layer 12 and n.sup.+ type substrate 11, the electrons are accelerated by the electric field E within depletion layer 20 so that they flow toward n.sup.+ type substrate 11 in the form of hot electrons. On the other hand, the holes are likewise accelerated by the electric field E within depletion layer 20 so that they flow toward p.sup.+ type gate region 13 in the form of hot holes. Part of the holes (hot holes) will flow into channel region 19 and n.sup.+ type source region 14.
The flow of holes (hot holes) resulting from the secondary avalanche breakdown into channel region 19 and n.sup.+ source region 14 in the forms of hot holes may cause the deterioration of voltage-withstanding property and destruction of the device. At the time of measurement of the drain-source breakdown voltage BV.sub.DSS in the way as illustrated in FIG. 2A, the presence of holes which flow into n.sup.+ type source region 14 can be observed as a source current Is.
It is predicted that the device destruction described above results from the discharge of energy, which holes (hot holes) generated by the secondary avalanche breakdown acquire from electric field E within depletion layer 20 when they flow into n.sup.+ type source region 14, as heat at the interface between n.sup.+ source region 14 and n.sup.- type epitaxial layer 12.